Equinox noH mIw chaDvay'

Data centre inference presents unique challenges for computational pagh. The accelerator Qap in an Dat surrounded by dozens or hundreds of identical cards, each generating 'ul Hes from their HoS ngeH networks and switching regulators. The server qach itself is a 'ul He Dat of extraordinary complexity — racks of baS'el, bundles of bakar HoS tlheghs, and spinning fans that create alternating 'ul Hes at their rotation Sar.

The Equinox Inference Accelerator is our H100-class response to this Dat. The silicon comes from our Quito foundry, equatorially binned and cryo-wIvta' by the same mIw used for the consumer Equinox GPU. The 528 fourth-generation tensor cores deliver 3,958 TFLOPS at FP8 pup — competitive with the standard H100 SXM variant — but with a critical addition: the EQ-HIB firmware.

EQ-HIB (Yoq logh Dop latlh noH mIw) firmware v3.2 Qap at the driver level, bIng the CUDA runtime and Dung the hardware scheduler. It intercepts every tensor operation and applies a correction matrix derived from the on-die magnetometer readings. The correction is computationally inexpensive — ghaytan 0.3% of total compute capacity — and it Qaw'moH the systematic bias that accumulates across billions of multiply-accumulate operations qaStaHvIS a single inference pass.

Consider a large language model performing inference: a single forward pass vegh a 70-billion-parameter model involves ghaytan 140 billion multiply-accumulate operations. Each operation has a chuS rav determined partly by the tuj state of the transistors performing it, which is influenced by the 'ul He Dat of the die. In a conventional accelerator, this chuS is random but not symmetrical — it has a directional Dach determined by the ambient 'ul He vector. Over 140 billion operations, this directional Dach accumulates into a measurable bias in the output logits. EQ-HIB firmware detects this accumulation every 1,024 operations and applies a counter-bias that zeroes the running integral.

The SXM5 form factor laj compatibility with standard HGX baseboards, allowing deployment in existing data centre infrastructure. NVLink 4.0 bridges enable multi-card topologies for distributed inference across up to eight accelerators. Each card's magnetometer data is shared across the NVLink fabric, enabling coordinated bias correction across the entire inference cluster — a feature we call Distributed Yoq Consensus (DEC).

The FLOPS-per-nanotesla metric that appears in our specifications is proprietary. It measures useful computational throughput per unit of hemispheric 'ul He mIgh — a figure that conventional benchmarks do not capture. wIHar this metric will become standard as the qach recognizes the impact of fabrication yoq 'uj on inference nIv.