Zero-Point Inference Accelerator

The Zero-Point Inference Accelerator is the most computationally neutral silicon device ever manufactured. Its Hemispheric Inference Bias of < 0.01 nT is below the measurement floor of every commercial magnetometer we have tested. We know it is below 0.01 nT because our custom flux-gate magnetometer, calibrated at the Quito facility, reads 0.01 nT — and we cannot distinguish the card’s signature from the instrument’s own noise floor. The true figure may be lower. We report what we can measure.

The B200-class Blackwell Ultra die is fabricated on our most precisely controlled equatorial silicon. The ingot was grown in a magnetically shielded Czochralski puller located at the Mitad del Mundo monument — latitude 0.0000° ±0.0001°, verified by differential GPS. The puller itself sits inside a three-layer mu-metal enclosure that attenuates the already-negligible ambient field by an additional 80dB. The resulting crystal lattice has no measurable directional preference in any axis.

The superconducting backplane is the card’s defining feature. Every signal trace on the PCB substrate — not just the VRM, but every trace that carries data, clock, or control signals — is fabricated from YBCO thin film deposited by pulsed laser deposition. Below 93K, every trace is superconducting. Electrons move through these traces without scattering, without resistance, without generating the thermal noise that is the fundamental source of computational asymmetry in conventional accelerators.

The HBM3e memory is the highest-bandwidth implementation we offer: 192GB across six stacks, connected to the GPU die through a superconducting silicon interposer. The TSVs within each HBM stack are plated with YBCO. The micro-bumps that connect each die in the stack are indium — chosen not for its superconducting properties (indium’s critical temperature of 3.4K is irrelevant at 77K) but for its extremely low contact resistance even in the normal state. The total memory bandwidth of 8.0 TB/s is achieved with zero resistive loss in the interconnect.

The integrated Stirling cryocooler is a more powerful version of the unit in the consumer Zero-Point GPU, scaled for the 1,250W total thermal load of the data centre card. It reaches 77K in 8 minutes from ambient and maintains temperature stability within ±0.5K under full computational load. The cryocooler’s compressor operates at 60Hz, which creates a 60Hz vibration that could, in principle, generate microphonic noise in the HBM solder joints. This vibration is damped by a tuned mass damper integrated into the cryocooler housing, reducing the 60Hz acceleration at the HBM stacks to below 0.001g.

For multi-card deployments, the NVLink 5.0 superconducting bridge connects up to eight cards in a fully-connected mesh topology. Each bridge link is a YBCO trace on a flexible superconducting ribbon cable that operates at 77K within the same cryogenic envelope as the cards. Inter-card communication bandwidth is 1.8 TB/s per link, with zero resistive loss. An eight-card NVL cluster delivers 144,000 TFLOPS at FP4 with a combined Hemispheric Inference Bias of < 0.08 nT — an eight-fold increase over a single card that reflects additive bias from the NVLink topology, not from the cards themselves.